Today is September 05, 2010

DURATION

DATE (From-To)

COURSE FEE

* In partnership with Advanced Science and Technology Institute of the Department of Science and Technology (ASTI-DOST)

At the end of this training, the participants are expected to understand the complete CPLD and FPGA design flow and be able to write hardware designs using VHDL that optimize CPLD and FPGA resources in both speed and area. Participants will be able to experience hands-on verification of their designs on the training kits, which will be provided. Laboratory exercises will be performed using Xilinx ISE and ModelSim Simulator.

COURSE OBJECTIVES:

At the end of the course, participants are expected to:

• Develop an understanding of the technologies and architectures of the programmable logic devices nowadays.
• Gain insight on the issues involved in effectively using programmable logic devices (PLD's) to implement a specific circuitry.
• Have the opportunity to use hardware description language to design, to gain hands-on experience in using EDA tools, and to realize designs on PLD's.

TARGET PARTICIPANTS:

Digital Design Engineers

PRE-REQUISITE SKILLS:

Basic VHDL language training

COURSE OUTLINE:

Day 1

• Introduction to FPGA Backend
• Introduction to FPGA and its design flow
• FPGA backend and its physical design issues
• Study of the Virtex Family FPGA

Laboratory Exercise : Design of an Arithmetic Logic Unit (ALU)

Day 2

VHDL Synthesis

• Overview
• Synthesis Design Flow
• Modeling for Synthesis
• Review : Combinational and Sequential Circuits
• Mapping VHDL to Hardware
• Simulation vs. Synthesis
• Good Coding Practices
• Synthesis Guidelines 
• Keys to Successful Synthesis

Laboratory Exercise : Synthesis of an ALU

Day 3

Place and Route and Download  
Laboratory Exercise : FPGA Implementation of an ALU