Today is September 05, 2010

DURATION

DATE (From-To)

COURSE FEE

* In partnership with Advanced Science and Technology Institute of the Department of Science and Technology (ASTI-DOST)

At the end of this three-day course the participants are expected to learn the syntax and semantics of the VHDL language and be able to code simple combinational and sequential circuits in VHDL.  Laboratory exercises will be performed using XilinxISE  and ModelSim Simulator.

COURSE OBJECTIVES:

At the end of the course, participants are expected to:

• Understand VHDL keywords, syntax and coding styles necessary for logic design.
• Understand and write VHDL models for combinational and sequential logic designs.

TARGET PARTICIPANTS:

Digital Design Engineers

PRE-REQUISITE SKILLS:

Basic knowledge of digital logic design

COURSE OUTLINE:

Day 1

• VHDL : Overview and Application Field
  • Applications of HDL, History, VHDL Concepts
  • Abstractions, Modularity and Hierarchy
    
• VHDL Language and Syntax
  • Literals, Identifiers, Naming Convention
  • Structural Elements 
  • Component Declaration, Instantiation
  • Signals, Attributes, Variables
  • Functions, Procedures
  • Data Types, Subtypes, Arrays, Concatenation, Aggregates
    
• Laboratory Exercise : Familiarization with the Xilinx ISE Webpack

Day 2

• Combinational Logic Design Using VHDL
  • Overview of Combinational Logic
  • VHDL Combinational Template
  • Concurrent and Sequential Statements
  • Examples
    
• Laboratory Exercise : Implementation of a Ripple Adder

Day 3

• Sequential Logic Design Using VHDL
  • Overview
  • General Model for Sequential Circuits
  • Flips-flops, Counters and Registers
  • Sequential Circuit Modes
  • Synthesis of Clock Mode Sequential Circuits
  • Sequential Statements
  • Variables
  • RTL Combinational Logic and Registers
    
• Laboratory Exercise : Implementation of a Sequence Detector