Today is September 05, 2010

DURATION

DATE (From-To)

COURSE FEE

This three-day training introduces the basic concepts and techniques of modern digital integrated circuit design.  Topics include an introduction to VLSI system, CMOS fabrication process, VLSI design flow and full-custom mask layout design.  Supplementary lectures on CMOS logic gates are also included to enable the trainees to perform the laboratory exercises.  The exercises are designed to provide first-hand experience in implementing digital IC blocks using freeware tools (Electricô VLSI Design System and WinSpice).  In order for the course to be beneficial, the trainees must have an understanding of electronic circuit fundamentals. 

COURSE OBJECTIVES         :             At the end of the course, participants are expected to: 

ß         appreciate the most important VLSI design concepts

ß         understand the full-custom IC design flow

ß         grasp the principles of mask layout design

ß         be capable of implementing simple CMOS logic circuits                                                                

TARGET PARTICIPANTS:  

ß          Engineering faculty who would like to explore and teach other fields in Electronics to add in their existing curriculum

ß          Engineering students who plan to pursue a career in microelectronics and would like to have a background on the full-custom IC design flow

ß          Engineers who are interested to upgrade their skills and design VLSI circuits using a CAD tool 

PRE-REQUISITE SKILLS      :             None  

COURSE OUTLINE                :

Day 1:

ß          Introduction to VLSI Systems

• Historical Perspective
• VLSI Design Principle
• Implementation Strategies
• EDA Tools 

ß          CMOS Fabrication Process

ß          Simplified Process Sequence

ß          Lithography

ß          NMOS Transistor Fabrication

ß          CMOS N-well Process 

ß          VLSI Design Flow

ß          Full-custom IC Design Flow

ß          Standard Cell-Based IC Design Flow

ß          From Mask Layout to Fabricated Chip

ß          Electric Schematic Tool Starter

ß          Laboratory Exercise 1:  CMOS Inverter Static Characteristics

ß          Laboratory Exercise 2: CMOS Inverter Dynamic Characteristics 

Day 2:

ß          Laboratory Exercise 3: CMOS NOR and NAND Gates

ß          Introduction to Full-custom Mask Layout Design

ß          CMOS Layout Mask Design Flow

ß          CMOS Layout Design Rules

ß          Stick Diagrams

ß          Electric Layout Tool Starter

ß          Laboratory Exercise 4: CMOS Inverter Layout 

Day 3:

ß          Laboratory Exercise 5: CMOS NOR and NAND Gates Layout

ß  Laboratory Exercise 6:  Half-Adder Design