Mr. Jose Redentor A. Glifonea is a Computer Engineering graduate at the University of the Philippines, Diliman. He is currently the team leader of the Digital Design Team of the Microelectronics Division of ASTI. He has accomplished several projects for the division, to wit: the FPGA Implementations of a 32-bit StrongARM-based RISC microprocessor core, the core's memory management unit (MMU), write and read buffers and the 512-byte mini-cache of the core's data cache.
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